- 基于NI Multisim 11的PLD/PIC/PLC的仿真設計
- 聶典 李北雁等編著
- 14字
- 2019-03-01 13:31:25
第2章 組合邏輯電路的仿真設計
2.1 邏輯運算
NI Multisim 11中“與”邏輯運算電路如圖1.2.1所示。
圖1.2.1 “與”邏輯運算電路
NI Multisim 11中產生的“與”邏輯運算的VHDL代碼如下所示。
---------------------------------------------------
--Source File:
--Sheet: _uc14e0e
--RefDes: PLD1
--Part Number:
--Generated By: NI Multisim
--
--Author: ni
--Date: Thursday, August 26 15:34:53,2010
---------------------------------------------------
---------------------------------------------------
--Use: This file defines the top-level of the design
--Use With File:
---------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library work;
use work._uc14e0e_pkg.ALL;
entity\_uc_uc14e0e\is
port(
IO1: in std_logic;
IO2: in std_logic;
IO3: out std_logic
);
end\_uc_uc14e0e\;
architecture behavioral of\_uc_uc14e0e\is
component AND2_NI
port(
B: in STD_LOGIC:=' X' ;
A: in STD_LOGIC:=' X' ;
Y: out STD_LOGIC:=' U'
);
end component;
component AUTO_IBUF
port(
I: in std_logic;
O: out std_logic
);
end component;
component AUTO_OBUF
port(
I: in std_logic;
O: out std_logic
);
end component;
signal\1\: std_logic;
signal\2\: std_logic;
signal\3\: std_logic;
begin
IO1_AUTOBUF: AUTO_IBUF
port map(I=>IO1, O=>\1\);
IO2_AUTOBUF: AUTO_IBUF
port map(I=>IO2, O=>\2\);
U1: AND2_NI
port map(A=>\1\, B=>\2\, Y=>\3\);
IO3_AUTOBUF: AUTO_OBUF
port map(I=>\3\, O=>IO3);
end behavioral;
NI Multisim 11中“與”邏輯運算電路的仿真實例。構建“與”邏輯運算的仿真實例電路，如圖1.2.2所示。
仿真波形如圖1.2.3所示。
圖1.2.2 “與”邏輯運算的仿真實例電路
圖1.2.3 “與”邏輯運算的仿真實例電路波形
NI Multisim 11中“6輸入或”邏輯運算電路如圖1.2.4所示。
圖1.2.4 “6輸入或”邏輯運算電路
NI Multisim 11中產生的“6輸入或”邏輯運算的VHDL代碼如下所示。
---------------------------------------------------
--Source File:
--Sheet: _uc1201c6_uca8f9351656216201d903b8f918fd07b9775358def
--RefDes: PLD1
--Part Number:
--Generated By: NI Multisim
--
--Author: ni
--Date: Thursday, August 26 15:54:29,2010
---------------------------------------------------
---------------------------------------------------
--Use: This file defines the top-level of the design
--Use With File:
---------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library work;
use work._uc1201c6_uc98f9351656216201d903b8f918fd07b977684VHDL_
uc24ee37801_pkg.ALL;
entity\_uc_uc1201c6_uc_uca8f9351656216201d903b8f918fd07b9775358def\is
port(
IO1 : in std_logic;
IO2 : in std_logic;
IO3 : in std_logic;
IO4 : in std_logic;
IO5 : in std_logic;
IO6 : in std_logic;
IO7 : out std_logic
);
end\_uc_uc1201c6_uc_uca8f9351656216201d903b8f918fd07b9775358def\;
architecture behavioral of\_uc_uc1201c6_uc_
uca8f9351656216201d903b8f918fd07b9775358def\is
component AUTO_IBUF
port(
I : in std_logic;
O : out std_logic
);
end component;
component AUTO_OBUF
port(
I : in std_logic;
O : out std_logic
);
end component;
component OR6_NI
port (
F : in STD_LOGIC := ' X' ;
E : in STD_LOGIC := ' X' ;
D : in STD_LOGIC := ' X' ;
C : in STD_LOGIC := ' X' ;
B : in STD_LOGIC := ' X' ;
A : in STD_LOGIC := ' X' ;
Y : out STD_LOGIC := ' U'
);
end component;
signal \1\ : std_logic;
signal \2\ : std_logic;
signal \3\ : std_logic;
signal \4\ : std_logic;
signal \5\ : std_logic;
signal \6\ : std_logic;
signal \7\ : std_logic;
begin
U1 : OR6_NI
port map( A => \4\, B => \5\, Y => \7\, C => \6\, D => \3\, E => \2\, F => \1\ );
IO1_AUTOBUF : AUTO_IBUF
port map( I => IO1, O => \5\ );
IO2_AUTOBUF : AUTO_IBUF
port map( I => IO2, O => \4\ );
IO3_AUTOBUF : AUTO_IBUF
port map( I => IO3, O => \6\ );
IO4_AUTOBUF : AUTO_IBUF
port map( I => IO4, O => \3\ );
IO5_AUTOBUF : AUTO_IBUF
port map( I => IO5, O => \2\ );
IO6_AUTOBUF : AUTO_IBUF
port map( I => IO6, O => \1\ );
IO7_AUTOBUF : AUTO_OBUF
port map( I => \7\, O => IO7 );
end behavioral;
NI Multisim 11中“6輸入或”邏輯運算電路的仿真實例如圖1.2.5所示。
圖1.2.5 “6輸入或”電路邏輯運算仿真實例