Notes on the Text

Part I

1. The objective is to be able to design a circuit from the basis of the published data, and know that it will function as predicted when the prototype is constructed.

目標是能夠依據公布的數據設計電路，并知道構建的樣機將具有預期的功能。

2. It is all too easy with linear circuits, which appear relatively simple when compared with today's complex logic arrangements, to ignore detailed performance parameters which can drastically reduce the expected performance.

對于線性電路而言，它們與現在的復雜邏輯電路結構相比看起來較為簡單，（因而在設計中）太容易忽視具體的性能參數了，這些參數可極大地削弱預期性能。

·本句主要結構：It is easy … to ignore …

·兩個which從句分別修飾circuits和parameters。

3. Consider a requirement for an amplifier having a voltage gain of 10 at 50 kHz driving into a 10 kΩ load.

考慮對于一個在50kHz頻率上電壓增益為10的放大器驅動10kΩ負載時的要求。

4. A common low-cost, internally frequency-compensated op amp is chosen; it has the required bandwidth at a closed-loop gain of 10, and it would seem to meet the bill.

選擇一個普通的帶有內部頻率補償的低價運放，它在閉環增益為10時具有所要求的帶寬，并且看來滿足價格要求。

5. But it will only produce a few volts output swing when the data clearly shows that the output should be capable of driving to within two or three volts of the power supply.

但是它只能產生幾伏的輸出擺幅，然而數據表卻清楚地顯示輸出應該能驅動達到電源的2～3V范圍以內（例如供電電壓是-10～+10V，則根據數據表輸出應能達到-8～+8V或-7～+7V）。

6. How many times has a circuit been designed using typical values, only to find that the circuit does not work because the device used is not typical?

有多少次是根據典型值設計好電路后卻發現只是因為使用的器件不典型而不能工作呢？

7. Clearly, if certain performance requirements are mandatory, then worst-case values must be used. In many cases, however, the desirability of a certain defined performance will be a compromise between ease of implementation, degree of importance, and economic considerations.

顯然，如果某些性能要求是強制性的，則一定要用最不利情況下的數值。然而在許多情況下，某一規定性能是否可取將在易實現性、重要性、經濟性之間進行平衡。

8. Simplicity is of the essence since the low parts count implementation is invariably cheaper and more reliable.

簡單極為重要，因為用較少元器件實現（的電路）必然更便宜也更可靠。

·low parts count implementation：采用零件少的實現方案。low count：低的計數，即數量少。parts：零件。

9. As an example of this judgment about worst-case design, consider a low-gain DC transducer amplifier required to amplify 10 mV from a voltage source to produce an output of l V with an accuracy of ±1% over a temperature range of 0～70℃.

作為最不利情況設計的例子，考慮一個低增益直流傳感器放大器，要求將電壓源輸出的10mV信號放大，產生1V的輸出，在0～70℃范圍內達到±1%的精度。

10. A closed-loop gain change of ±1% implies that the loop gain (as explained later) should change by less than ±100% for a closed-loop gain of 100.

閉環增益±1%的變化意味著環路增益（將在下面說明）的變化在閉環增益為100時應該小于±100%。

11. Many op amp specifications include only typical values for offset voltage drift; this may well be in the order of 5 μV/℃, with an unquoted maximum for any device of 30 μV/℃.

許多運放技術指標僅僅給出補償電壓偏移的典型值，這很可能會在5 μV/℃的數量級，而未給出任何器件可以達到的最大值30 μV/℃。

Part Ⅱ

1. It is simply a set of flip-flops (usually D latches or RS flip-flops) connected together so that the output of one becomes the input of the next, and so on in series.

它就是一組觸發器（通常是D鎖存器或RS觸發器）聯在一起，使得其中一個觸發器的輸出成為下一個的輸入，以此形成一串。

2. It is called a shift register because the data is shifted through the register by one bit position on each clock pulse.

它被稱為移位寄存器，因為數據在每一個時鐘脈沖的作用下通過寄存器移動一位。

3. On the leading edge of the next clock pulse, the contents of the first flip-flop is stored in the second flip-flop, and the signal which is present at the DATA input is stored is the first flip-flop, etc.

在下一個時鐘脈沖的前沿，第一個觸發器的內容被存放到第二個觸發器中，而在數據輸入端的信號則存放在第一個觸發器中，以此類推。

4. The parallel loading of the flip-flop can be synchronous (i.e., occurs with the clock pulse) or asynchronous (independent of the clock pulse) depending on the design of the shift register.

觸發器的并行加載可以是同步的（即在時鐘脈沖到達時發生），或者異步的（不依賴于時鐘），取決于移位寄存器的設計。

5. The flip-flops are attached to each other in a way so that the output of one acts as the clock for the next, and so on. In this case, the position of the flip-flop in the chain determines its weight; i.e., for a binary counter, the “power of two” it corresponds to.

觸發器以這樣的方式相互連接，使得一個觸發器的輸出成為下一個的時鐘，以此類推。這樣，觸發器在鏈中的位置決定了它的權重，即對于二進制計數器而言就是它所對應的2的冪。

6. Note that a set of lights attached to Q1, Q2, Q3would display the numbers of full clock pulses which had been completed, in binary (modulo 8), from the first pulse.

注意，一組接在Q1、Q2、Q3上的燈泡將以二進制（模8）形式顯示從第一個脈沖開始已完成的完整時鐘脈沖數。

7. Therefore there will be a slight time delay, due to the propagation delay of the flip-flops between the time one flip-flop changes state and the time the next one changes state, i.e., the change of state ripples through the counter, and these counters are therefore called ripple counters.

因此將略有時延，這是由一個觸發器改變狀態到下一個觸發器改變狀態之間的傳播延遲造成的，即狀態的變化像波紋一樣傳過計數器，因而這些計數器被稱為波紋計數器。

8. By the use of preset and clear inputs, and by gating the output of each T flip flop with another logic level using AND gates (say logic 0 for counting down, logic 1 for counting up), then a presetable up-down binary counter can be constructed.

利用預置和清零端，通過用與門將每一個T觸發器的輸出與另一個邏輯電平做邏輯運算（例如0為向下計數，1為向上計數），則可構成可預置的可逆二進制計數器。

9. The output of one flip-flop is the input to the next; the state changes consequently“ripple through” the flip-flops, requiring a time proportional to the length of the counter.

一個觸發器的輸出是下一個的輸入，因而狀態的變化以波動形式通過各個觸發器，所需時間與計數器的長度成正比。

10. This can be easily done by noting that, for a binary counter, any given digit changes its value (from 1 to 0 or from 0 to 1) whenever all the previous digits have a value of 1.

這很容易做到，注意到對于二進制計數器，只要所有前面的數字都是1，任何給定的數字都會改變它的值（從1變為0，或者從0變為1）。

Part Ⅲ

1. Control voltage on the VCO changes the frequency in a direction that reduces the phase difference between the input signal and the local oscillator.

壓控振蕩器的控制電壓使頻率朝著減小輸入信號與本地振蕩器之間相位差的方向改變。

2. When the loop is locked, the control voltage is such that the frequency of the VCO is exactly equal to the average frequency of the input signal.

當鎖相環處于鎖定狀態時，控制電壓使得壓控振蕩器的頻率正好等于輸入信號頻率的平均值。

3. The task of a phase-lock receiver is to reproduce the original signal while removing as much of the noise as possible.

鎖相接收機的作用是重建原信號而盡可能地去除噪聲。

4. If the original signal is well behaved (stable in frequency), the local oscillator will need very little information to be able to track, and that information can be obtained by averaging for a long period of time, thereby eliminating noise that could be very large.

如果原信號質量好（頻率穩定），本地振蕩器只需要極少信息就能實現跟蹤，此信息可通過長時間的平均得到，從而消除可能很強的噪聲。