Notes on the Text

Part I

1. Roughly speaking, the transistor can be likened to an electronically controlled valve whereby energy applied to one connection of the valve enables energy to flow between two other connections.

粗略地說，晶體管好似一種電子控制閥，由此加在閥一端的能量（電壓）可以使能量（電流）在另外兩個端之間流動。

2. Consult a periodic table of elements in a college chemistry textbook, and you will locate semiconductors as a group of elements separating the metals and nonmetals.

查閱大學化學書中的元素周期表，你會查到半導體是介于金屬與非金屬之間的一類元素。

3. Phosphorous and boron are two elements that are used to dope N-type and P-type silicon, respectively.

N型硅半導體摻入磷元素，而P型硅半導體摻入硼元素。

4. The resulting small chip of semiconductor material on which a transistor or diode is fabricated can be encased in a small plastic package for protection against damage and contamination from the outside world.

半導體材料上制作晶體管或二極管所形成的小芯片用塑料封裝以防損傷和被外界污染。

Part Ⅱ

1. As feature sizes have shrunk and design tools improved over the years, the maximum complexity (and hence functionality) possible in an ASIC has grown from 5000 gates to over 100 million.

隨著特征尺寸的逐年縮小和設計工具的改進，ASIC中的最大復雜度從5000個門電路增長到了1億個門電路，因而功能也有了極大的提高。

2. The non-recurring engineering cost (the cost to setup the factory to produce a particular ASIC) can run into hundreds of thousands of dollars.

不能循環的工程費用（建立工廠生產特定ASIC的成本）可能會達到數十萬美元。

3. The general term application specific integrated circuit includes FPGAs, but most designers use ASIC only for non-field programmable devices and make a distinction between ASIC and FPGAs.

專用集成電路這一通用名詞也包括FPGA，但是大多數設計者僅將ASIC用于非現場可編程的器件，將ASIC和FPGA兩者區別開來。

4. While third party design tools were available, there was not an effective link from the third party design tools to the layout and actual semiconductor process performance characteristics of the various ASIC manufacturers.

盡管有第三方設計工具，但第三方設計工具和不同的ASIC制造商的布線以及實際半導體工藝過程的性能之間卻缺乏有效的聯系。

5. Every ASIC manufacturer could create functional blocks with known electrical characteristics, such as propagation delay, capacitance and inductance; that could also be represented in third party tools.

每個ASIC制造商都可以創造他們自己的具有已知電性能的功能塊，如傳播延遲器、電容、電感，這些都可以用第三方工具來表示（實現）。

6. Standard cell design fits between Gate Array and Full Custom design in terms of both its NRE (Non-Recurring Engineering) and recurring component cost.

標準單元設計使門陣列和全定制設計之間在一次性投入的工程費用和循環元件成本方面相互適應。

·Non-recurring engineering (NRE) refers to the one-time cost of researching, designing, and testing a new product.

7. These steps, implemented with a level of skill common in the industry, almost always produce a final device that correctly implements the original design, unless flaws are later introduced by the physical fabrication process.

以工業界普通的熟練水平實現的這些步驟幾乎總是產生能正確實現原設計的最終器件，除非后來在物理制造過程中引入了缺陷。

8. These constructs are taken from a standard-cell library consisting of pre-characterized collections of gates such as 2 input nor, 2 input nand, inverters, etc.

這些構成的元素是從一個標準單元庫中得到的，這個庫由事先規定好的門電路集合構成，例如2輸入或非門、2輸入與非門、非門等。

9. The significant difference is that Standard Cell design uses the manufacturer's cell libraries that have been used in hundreds of other design implementations and therefore are of much lower risk than full custom design.

重要的差別在于標準單元設計使用制造商的單元庫，這些庫已用于數以百計的設計實現，因而比起全定制設計來風險小得多。

10. Gate array design is a manufacturing method in which the diffused layers, i.e. transistors and other active devices, are predefined and wafers containing such devices are held in stock prior to metallization, in other words, unconnected.

門陣列設計是一種制造方法，事先定義好擴散層（晶體管和其他有源器件），包含這些器件的晶片在金屬化之前被庫存，也就是說先不進行連接。

11. Gate array ASIC is a compromise as mapping a given design onto what a manufacturer held as a stock wafer never gives 100% utilization.

門陣列ASIC是一種折中方案，因為將某一給定的設計與制造商庫存的晶片相對應總是不可能達到100%利用率的。

·as mapping … never gives … 表示原因。

12. Pure, logic-only gate array design is rarely implemented by circuit designers today, replaced almost entirely by field programmable devices such as FPGAs, which can be programmed by the user and thus offer minimal tooling charges, marginally increased piece part cost and comparable performance.

現在電路設計者已經很少采用純粹的邏輯門陣列設計，而幾乎都代之以FPGA之類的現場可編程器件了。這些器件可由用戶編程，使工具作業費用最低，以略為提高的零件價格獲得可比的性能。

13. Today gate arrays are evolving into structured ASICs that consist of a large IP core like a processor, DSP unit, peripherals, standard interfaces, integrated memories SRAM, and a block of reconfigurable uncommitted logic.

現在門陣列正在發展為結構化ASIC，其中包含很大的IP內核，如處理器、DSP單元、外圍設備、標準接口、集成SRAM存儲器以及一組可重新設置的未確定功能的邏輯單元。

·IP core (intellectual property core)：預先設計好、可復用、有知識產權的硬件或軟件塊。

14. The disadvantages can include increased manufacturing and design time, increased non-recurring engineering costs, more complexity in the CAD system and a much higher skill requirement on the part of the design team.

缺點包括增加的制造和設計時間，增加的不可循環工程成本，更復雜的CAD系統，以及對設計團隊熟練程度高得多的要求。

15. However, the basic premise of a structured ASIC is that both manufacturing cycle time and design cycle time are reduced compared to cell-based ASIC by virtue of there being pre-defined metal layers and pre-characterization of what is on the silicon.

不過結構化ASIC的基本前提是，由于有事先定義的金屬層和事先規定了硅片上包含的內容，制造周期和設計周期相對于基于單元的ASIC都有所減少。